Understanding VLSI Design
CMOS VLSI Design
edit- Introduction (pdf)
Design Objects
editDevice
edit- MOSFET-1 : Capacitors (pdf)
- MOSFET-2 : Operation Modes (pdf)
- MOSFET-3 : Capacitance Types (pdf)
- MOSFET-4 : Body Effect, Latchup (pdf)
- MOSFET-5 : Energy Band Diagrams (pdf)
- (Energy Band)
- Inverter-1 : Inverter, VTC, Noise Margin (pdf)
- Inverter-2 : nMOS Linear Model, nMOS Resistance, nMOS Capacitance (pdf)
- Inverter-3 : Inverter Fall Delay & Rise Delay, Propagation Delay, and Gate Delay (pdf)
- PassTr : Pass Transistor (pdf)
Interconnect
edit
Design Tools
editSpice Model & Simulation
edit- Spice (pdf)
Layout & Simulation
edit- Electric (Static Free Software)
- LT Spice (Linear Technology)
Design Constraints
editDelay
editLogic Level Delay Overview
CMOS Level Delay
- Delay-1 : Transistor Sizing (pdf)
- Delay-2 : Logical Effort (pdf)
- Delay-3 : Logical Effort Applications (pdf)
- Delay-4 : Device Delay (pdf)
- Delay-5 : Inverter Chain Delay (pdf)
- Delay-6 : Multistage Delay (pdf)
- Delay-7 : Elmore Delay (pdf)
- Delay-8 : Delay Model (pdf)
- Delay-9 : Wire Delay (pdf)
- Delay-A : Logical Effort and Gate Sizing
Power
editLogic Level Power Overview
CMOS Level Power
- Power-1 (pdf) : Power
Design Techniques
editSimple Logic Gate Design
editNAND Gate Design
- NAND (pdf)
NOR Gate Design
- NOR (pdf)
Combinational Circuit Design
editLogic Level Combinational Circuit Design Overview
- Background (pdf)
CMOS Level Combinational Circuit Design
- Combinational-1 : Pull Up Network, Pull Down Network, AOI, OAI (pdf)
- Combinational-2 : Decoder, Mux, Tristate Inv (pdf)
- Combinational-3 : Standard Cell, Design Flow (pdf)
Sequential Circuit Design
editLogic Level Sequential Circuit Design Overview
CMOS Level Sequential Circuit Design
- Sequential-1 : Modern Latch & Flipflop(pdf)
- Sequential-2 : Classical Latch & Flipflop(pdf)
- Sequential-3 : Latch & Flipflop Timing Constraints(pdf)
- Sequential-4 : Enable, Reset, Set (pdf)
Other MOS Logic Family Design
edit- Static-1 : Pseudo-nMOS, Transmission Gate (pdf)
- Static-2 : Skewed Inverters, Ratioed Logic (pdf)
- Dynamic-1 : Footed, Unfooted, Domino Logic (pdf)
- Dynamic-2 : Logical Effort of Dynamic Logic Gates (pdf)
Datapath Design
editRipple Carry Adder
Carry-Lookahead Adder
Carry Save Adder
- Logic Level Analysis (pdf)
- VHDL Implementations
- CMOS Level Analysis
Multiplier
Memory Array Subsystem Design
editLogic Level Overview
- Background (pdf)
- DRAM Memory (pdf)
- For DRAM, SDRAM, DDR, see B. Jacob's lecture notes on umd
- For a simple computer architecture, see Tiny CPU example
- TinyCPU Architecutre Timing Diagrams
CMOS Level
Logic Array Subsystem Design
editLogic Level Overview
CMOS Level
Design Issues
editScaling
editClock & Power
editIO
editPackage
edit
See also
- Understanding CMOS Design
- The necessities in Digital Design
- The necessities in Computer Design
- The necessities in Computer Architecture
- The necessities in Computer Organization
- Understanding Arithmetic Circuits
- Understanding Low Power Design
- [Understanding Arithmetic Circuits]]
- Understanding FPGA Design
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