The necessities in SOC Design
Overview
edit- SoC in the wikipedia pages (pdf)
Fabrication of VLSI Circuits
edit- CMOS Fabrication (pdf)
Device Level Design
edit- Digital Implementation (pdf) - ASIC, FPGA
- Analog Implementation (pdf) - Linear IC, Power IC, RF IC, Mixed Signal IC
Performance Metrics
editDevice Level Design Tools
edit- Spice Simulator
- VLSI CAD tools - Layout, Floorplanning, Placement and Routing, Physical Verification (LVS/DRC/ERC)
Transistor Level Design
editPerformance Metric
editDesign Issues
edit- Clock
- PLL & DLL
- I/O
Transistor Level Design Tools
edit- Spice
Gate Level Design
editPerformance Metric
editDesign Issues
edit- Static Timing Analysis
- Scan and Boundary Scan Cells
- Formal Verification
Gate Level Design Tools
edit- Verilog
- VHDL
- Static Timing Analysis
- Formal Verification
RTL Level Design
editPerformance Metric
edit- Estimation of
- Gate Count
- Critical Path
- Power
- Latency
- Throughput
Design Issues
edit- Partitioning and Coding Style
- Constraining Designs
- Optimizing Designs
- Design for Test (DFT)
- Pre-layout & Post-layout Simulation
RTL Design Tools
edit- Verilog
- VHDL
- Logic Synthesis
Architecture Level Design
editBackground: Tiny CPU Examples
edit
- - Cache Memory
- - Virtual Memory
- Readings (pdf)
- Interconnecting Buses
- - AMBA AHB & APB
- Readings (pdf)
Design Issues
edit- Memory Hierarchy
- Storage and I/O
- Instruction Level Parallelism
- Data Level Parallelism
- Thread Level Parallelism
Design Tools
edit- ADL (Architecture Design Language)
- - LISA, EXPRESSION, nML, ArchC
- SystemC TLM (Transaction Level Modeling)
System Level Design
edit- IP : OCP-IP, OpenCore
Typical SOC's
edit- Embedded System
- MPSOC
- NoC
Design Issues
edit- Transaction Level Modeling
- Hardware Software Partition
- Hardware Software Co-simulation
- Integration of Hardware IP Blocks
- Integration of Software IP Modules
- FPGA Based Emulation Platform
Design Tools
edit- High-Level Synthesis
- HVL (High-Level Verification Language)
- - SystemC Verifcation (SCV) (See "SystemC programming in plain view")
- - SystemVerilog
- Mixed Signal
- - VHDL-AMS
- - Verilog-AMS
- - SystemC-AMS
Design Flow
editHW/SW Design Examples : Traffic Controller Design
edit- HW/SW Implementation Overview (pdf)
Implementation in Hardware
Implementation in Software
- SW Implementation Without an OS (Bare Machine)
- SW Implementation with an RTOS (pdf)
RTL / Logic Level Design
edit- Logic Synthesis
- Logic Simulation
- Logic Timing Verification
- Logic Power Verification
- Test Synthesis
- Test Verification
- Testbench
- Code Coverage
- Equivalence Check
- Timing Verification
- Design Constraint
- STA (Static Timing Analysis)
- Scan Chain
- Back Annotation
- ATPG (Automatic Test Pattern Generation)
Physical Design
edit- Floorplanning
- Placement
- Routing
- Power Network
- Clock Distribution
- Physical Verification
- DRC (Design Rule Check)
- DV (Design Verification)
- GV (Geometry Verification)
- LVS (Layout Versus Schematic)
- SV (Schematic Verification)
Printed Circuit Board
edit
Test
edit- Design For Test
- ATPG (Automatic Test Pattern Generation)
- Analog and Mixed Signal Test
- JTAG (Joint Test Action Group) IEEE 1149.1
- Embedded Core Test IEEE 5000
- test access mechanisms (TAMs)
- Core test language (CTL)
Logical Verification
edit- Assertion Based Verification
- Transaction Level Models
- Formal Property Verification
2016 Spring Class
edit- Some useful links in VLSI design (1.pdf, 2.pdf)
- SystemC Projects (1.pdf) updated
- SystemC Installation Guide (pdf)
- OpenRISC ISS or1ksim Installation Guide (pdf)
References
edit- The necessities in Digital Design
- The necessities in Computer Design
- The necessities in Computer Architecture
- The necessities in Computer Organization
asic-world.com
For ASIC design flow, See
ASIC design flow (lth.edu)
For Tiny CPU, See
Tiny CPU
For general buses, See
PCI bus
general buses
old buses
For AMBA, See
Embedded Processor & AMBA
AMBA overview
For DDR, See
DDR overview
DDR
For UART, See
UART Overview
ARM UART Notes
For DMA, See
DMA OVerview
DMA & IO
DMA & OS
For Embedded Programming, See
Embedded Programming
Discovering STM32 microcontroller
For TLM, See
TLM Overview
TLM
TLM & AMBA
For the final,
Computer Arch
VHDL Primer (upenn.edu)
ASIC design flow (lth.edu)
Tiny CPU
Memory
DRAM
GPIO, UART, DMA, Int/Poll
UART Overview
GPIO Programming
AMBA Bus
ARM
TLM
TLM