Ioannis Kotleas s122576
Chatzigeorgakidis Georgios s121078
Dean Roy Humphreys s120971
Tobias Bennike Aagren s112345
Short presentation and comparison of instruction set characteristics for
- Intel 8008
- MIPS32 (1981)
- RTX 2000
Intel 8008 8-bit parallel CPU (1972)Edit
Intel 8008 was an 8-bit (byte-oriented) parallel microprocessor that used an accumulator, six 8-bit index registers, a 14-bit program counter and seven 14-bit registers in an address stack, used internally to store program and subroutine addresses. The 14-bit program counter provides direct access to 16 Kilobytes of memory. Two of the six 8bit registers mentioned before provide indirect memory addressing capability. The Instruction Set of Intel 8008 uses the 8-bit accumulator in order to execute the instructions through an Arithmetic Logic Unit (ALU). The first operand for the ALU is the 8-bit accumulator, passed on to a temporary register, while the second one is either an index register or an immediate in the instruction or a value read from memory and stored in the second 8-bit temporary register. The 8008 chip did not meet the Computer Terminal Corporation (CTC) performance goals and was used later in calculators, as well as in the first commercial Personal Computers.
- One 8-bit instruction register
- The scratch pad memory (seven 8-bit registers)
- ◦ One 8-bit accumulator
- ◦ Six 8-bit index registers
- Address stack (eight 14-bit registers)
- ◦ One 14-bit program counter
- ◦ Seven 14-bit for address storage for nesting subroutines up to seven levels
- Two 8-bit temporary registers (The operands of the ALU)
- One 8-bit parallel Arithmetic Logic Unit (ALU) that supports addition, subtraction and logical operations
- 16 Kilobytes of memory
- Input and output buffers
- 500KHz clock
- 20 μs average instruction cycle time
Instruction Set/Instruction FormatEdit
- 48 Instructions with three different instruction formats of 1, 2 or 3 bytes in length
- ◦ 1 byte – opcode :register to register, memory reference, I/O arithmetic or logical, rotate or return instructions
D7 D6 D5 D4 D3 D2 D1 D0 opcode
- ◦ 2 bytes – opcode and operand: Immediate mode instructions
D7 D6 D5 D4 D3 D2 D1 D0 opcode D7 D6 D5 D4 D3 D2 D1 D0 operand
- ◦ 3 bytes – opcode and 14 bit address: JUMP or CALL instructions
D7 D6 D5 D4 D3 D2 D1 D0 opcode x x D5 D4 D3 D2 D1 D0 LOW address D7 D6 D5 D4 D3 D2 D1 D0 HIGH address
- 5-cycle computation per byte of instruction
- 5 instruction groups
- ◦ Index register instructions: Load data to registers, load data immediate, increment/decrement index register
- ◦ Accumulator group instructions: ALU index register instructions, ALU operations with memory, rotate instructions
- ◦ Program Counter and stack control instructions: Return instructions, restart instruction
- ◦ Input/Output instructions: INP, OUT
- ◦ Machine Instruction: Halt Instruction
- Register indirect
MIPS Technologies MIPS32 (1981)Edit
MIPS32 is a 32-bit revision of the Microprocessor without Interlocked Pipeline Stages (MIPS) Instruction Set Architecture (ISA). It is a Reduced Instruction Set Computing architecture (RISC) developed by the MIPS Technologies. RISC architecture is in an attempt to reduce the complexity of the ISA and hence increase the speed. MIPS belongs to the load-store (register-register) type of architecture and relies heavily on registers, which makes it extremely fast but increases the instructions required for more complex operations. However, this setup lends itself well to pipelining and studies show that multiple simple instructions are more effective on average than more complex instructions that take a longer time to execute.
- MIPS uses a fixed-length instruction of 32 bits
- Each instruction can have a maximum of 3 operands, all of which are register-based
- ◦ No operation can be done on a value in memory, a load/store operation must be executed to move the data around
- 32-bit wide (1 word) registers
- 32 General Purpose Registers (GPR)
- Register $0 has a constant value of zero
- Register $1 is reserved for the assembler to handle pseudo-instructions
- Two special registers, HI and LO which are used for multiplication overflow
- One 32-bit Arithmetic Logic Unit (ALU) that supports addition, subtraction and logical operations
Instruction Set/Instruction formatsEdit
MIPS has three instruction formats as shown in the table below:
- R-Type instructions perform operations on registers (i.e. add, sub, xor…)
- I-Type instructions perform immediate operations such as adding constants and checking for equality (addi, subi, beq…)
- J-Type instructions are jump instructions which move the Program Counter (PC) to different locations in the program (j, jal…)
MIPS supports 3 different addressing modes:
- Base + Displacement
RTX 2000 is a 16-bit microcontroller designed to solve problems connected with embedded real-time systems. It is an improvement on Novix stack machines which could directly execute the Forth programming language. RTX 2000 implements subroutine calls in a way that they execute in one machine cycle.
- RTX 2000 uses a fixed-length instruction of 16 bits (with the exception of long literals, which uses 16 bits for the instruction and 16 bits for the literal value).
- RTX 2000 is a stack machine based on two-stack architecture.
- Implements 2 stacks of 256 words.
- One data stack and one return stack.
- ◦ Data stack is used for expression evaluation and subroutine parameter passing.
- ◦ Return stack is used for subroutine return address storage and for loop counter storage
- 8 16-bit internal registers (TOP, NEXT, IR, PC, CR, I, MD, SR)
- ◦ TOP has the top item of the parameter stack where NEXT contains the second item.
- ◦ IR has the executing instruction, where PC contains the address for the next instruction to be executed.
- ◦ I is the Index Register
- ◦ MD and SR are used as intermediate values for calculations.
Instruction Set/Instruction formats/Instruction ClassesEdit
RTX 2000 has one general instruction format:
|Class (12-15)||ALU(8-11)||SC(6-7)||Return bit (5)||Data (0-4)|
In the four most significant bits of the instruction the class type is indicated:
|8-9||Branches and loops|
|11||Register and short literal operations|
|12||User memory access|
|14||Memory access by word|
|15||Memory access by byte|
The following table summarizes the above Instruction Set Architectures for reasons of comparison.
Instruction Set Architecture
led to CISC
Inspired by RISC
6 general 8-bit registers
Accumulator and temporary operand registers
8 internal 14-bit registers
32 general + 2 special
Variable 1, 2 or 3 bytes
|No of Instructions||
Intel 8008 is an ancestor of Complex Instruction Set Computing (CISC), meaning that it can execute multiple-step operations with one instruction. However, this technique is not very well welcomed by the compiler developers because it introduces complexity. On the other hand, MIPS is a Reduced Instruction Set Computing architecture (RISC). Despite the fact that it may need more than one step for some operations, its simplicity attracts many compiler developers. The lost speed is gained due to the fast access to 32 general usage registers which can be utilized to store local variables and reduce therefore load-store operations and to the use of fixed-size instructions (Intel 8008 uses variable-size instructions). This allows for easy fetching and decoding of instructions and greatly simplifies pipelining. However, a fixed instruction length can cause limitations for instructions that require more bits than available, but these instructions are known to occur less frequently and hence prove less of an issue. Also, some instructions require less than 32 bits and in these cases bits are essentially wasted. MIPS has 32 General Purpose Registers, which simplifies even more the creation of the compiler, as the developer will always have enough registers available for the operations. The simplicity of MIPS is also apparent in the Instruction Formats.
1. 8-Bit Parallel Central Processor Unit Users Manual, Intel Corporation 1972
2. MIPS32® Instruction Set Quick Reference ()
3. The Harris RTX 2000 Microcontroller ()
4. Computer Architecture: A Quantitative Approach, Fifth Edition, John L. Hennessy and David A. Patterson, Morgan Kaufmann, 2012