Computer Architecture Lab/SS2013/GROUP2 LAB1
The microprocessors reviewed are Zilog Z80, MOS 6502 and Intel 8086.
Zilog Z80 edit
The Zilog z80 microprocessor has an 8 bit design. It was developed in 1976 and was widely used in desktop and embedded computer designs. Many East European manufacturers made unlicensed copies of z80. This enabled a small company's product to gain acceptance in the world market. The Z80 took over from the 8080 in the processor market and became one of the most popular 8-bit CPUs.
Features edit
- Enhanced instruction set including bit manipulation, block move, block I/O, and byte search instructions.
- IX and IY index registers with instructions for direct base+offset addressing
- Single 5 volt power supply and single-phase 5 V clock
- A built-in DRAM refresh mechanism that would otherwise have to be provided by external circuitry
- Non-multiplexed buses
- Two separate register files
Registers edit
- Dual-register set
- 8-bit registers, which are coupled to provide 16-bit versions
Instructions edit
Each instruction is executed in steps that can take between three and six clock periods. Many instructions actually end during the first step of the next instruction which is known as a fetch/execute overlap. Possible instructions in z80 are:
- Add
- Subtract
- Logical AND
- Logical OR
- Logical Exclusive OR
- Compare
- Left or Right Shifts or Rotates (Arithmetic and Logical)
- Increment
- Decrement
- Set Bit
- Reset Bit
- Test bit
The Z80 uses 252 out of the available 256 codes as single byte opcodes . The four remaining codes are used extensively as opcode prefixes. Z80 has a large number of permutations of instructions and registers. Zilog categorizes these into 158 different "instruction types".
References edit
MOS 6502 edit
The MOS Technology 6502 is an 8-bit CISC Microprocessor with a 16-bit address bus released in XXXX. Featured in the Apple I and II, along with the BBC Micro, Commodore 64 and NES, the MOS 6502 is often attributed with starting the Personal Computer revolution.
Features edit
The MOS 6502 features an Accumulator based ISA. Besides an 8-bit accumulator, the MOS 6502 has two index registers (X and Y), a 16-bit Program Counter (arranged into two 8-bit register, PCH and PCL), a 9-bit Stack Pointer (MSB set to 1), a Status Register and an Instruction Register. The Index registers can be used in indexed addressing instructions, and can be incremented and decremented. The MOS 6502 can only access 8 bytes at a time, while still supporting a 16-bit address range. Hence the MOS 6502 stores the program counter in a high a and a low register using a Little Endian byte order. Since the Stack Pointer is only 9-bits wide, and the msb fixed to one, the Stack Pointer can address any address between 0x100 and 0x1FF. The status register contains the status of the processor, and thus contains flags for the ALU. Later processors added more registers and expanded the stack pointer to a full 16-bit.
Instructions edit
The instructions are divided into Data moving, Arithmetic, Logic, Control transfer, and Other instructions. In additions to standard integer operations the MOS 6502 also supports decimal operations by setting a flag in the Status Register.
Addressing edit
Accumulator Addressing - A One byte instruction which manipulates the data in the Accumulator.
Immediate Addressing - A Two byte instruction. First byte is the Operator, second is the Operand.
Absolute Addressing - A Three byte instruction. Second byte is the LSB while the third is the MSB.
Zero Page Addressing - A Two byte instruction. Second byte is appended to a zero address. This addresses the Zero Page (range 0x00 to 0xFF).
Indexed Zero Page Adressing - Immediate value is added to either index register. Any carry into the high 8 bits is dropped.
Indexed Absolute Addressing - Same as previous, however with carry into the upper 8 bits.
Implied Addressing - Address of operand is implied in instruction.
Relative Addressing - A Two byte instruction. The second byte (encoded as 2's complement) is added to the program counter.
Indirect Indexed Addressing - Contents of Index X is is added to the second byte of the instruction, pointing to an address in the Zero Page. On this address is the lower end of the effective address, and the next address in the Zero Page holds the upper end of the effective address.
Indexed Indirect Addressing - The second byte of the instruction points to an address in the Zero Page. Contents on this address is added to Index Y (the carry is added to the next address in Zero Page). This is now the effective address.
Absolute Indirect - The Second and the Third byte of the instruction contain the lower end and upper end (respectively) of an address where the content is to be loaded into the PCL register. The next address is loaded into the PCH register.
References edit
Intel 8086 edit
The 8086 is a 16-bit CISC microprocessor developed and produced by Intel. It was introduced to the market in 1978, and laid the, suspectably unintended, foundations to the modern x86 processors, such as the Petiums, Core and i-series.
Instruction set edit
Encoding of the instructions are of variable word length
The 8086 did support floating point arithmetic, but could be connected to a co-processor that did. In later revisions of the architecture, the co-processor was added as part of the architecture. Other than that, the usual class of arithmetic, logic and control instructions are available. A small twist on the classical arithmetic, is that there are separate instructions for signed numbers. In the class of more special-purpose instructions, we find;
- AAM (ASCII adjust AX after multiplication )[3]
- PUSH and POP that works directly on the stack
- LOCK for locking the bus, useful for implementing atomic actions
It uses instruction pre-fetching, and fetches can overlap execution in a very basic pipelining fashion.
Branches are based on the bits in the status register, and do not require an extra cycle for loading a register.
Registers edit
Eight 16-bit registers are available with four registers accessible as two 8-bit registers (E.g. AX is also accessible is AH and AL, respectably A-High and A-Low). There is a separate register for instruction pointer and status.
A figure adapted from [2] is shown below, and outlines the registers and their usage.
Main registers ------------ | AH | AL | or AX (primary accumulator) ------------ | BH | BL | or BX (base, accumulator) ------------ | CH | CL | CX (counter, accumulator) ------------ | DH | DL | DX (accumulator, other functions) ------------
Index registers ------------ | SI | Source Index ------------ | DI | Destination Index ------------ | BP | Base Pointer ------------ | SP | Stack Pointer ------------
Status register -------------------------------------------------- |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0 | (bit position) -------------------------------------------------- | -| -| -| -| O| D| I| T| S| Z| -| A| -| P| -| C | Flags --------------------------------------------------
Segment register ------------ | CS | Code Segment ------------ | DS | Data Segment ------------ | ES | ExtraSegment ------------ | SS | Stack Segment ------------
Instruction pointer
------------ | IP | Instruction Pointer ------------
Addressing edit
The Intel uses a segmented memory model, mapping processes into memory segments. This is apposed to using paging, where memory pages belong to a process, and can swapped in and out in less portions than segments. Segmentation requires you to swap out the entire segment. Furthermore, it only addresses 64k, so in to able to access addresses beyond this area, you would need to manipulate the segment register.
The architecture supports a variety of addressing modes that can be combined to as much as 17 different addressing modes[1], but the base ones are;
- Displacement-only
- Base
- Displacement plus base
- Base plus indexed
- Displacement plus base plus indexed