Welcome to the Wikiversity content-development project for the Verilog language.

Verilog Course
Completion status: this resource is a stub, so not much has been done yet.
Type classification: this resource is a course.
Educational level: this is a tertiary (university) resource.
Subject classification: this is an engineering resource.

Introduction edit

Verilog is a Hardware description Language (HDL) originally began as a proprietary HDL of Cadence Design Systems. But Cadence transferred control of Verilog to a consortium of companies and universities known as Open Verilog International (OVI) as a step leading to its adoption as an IEEE standard.

Lessons edit

Introductory Lessons edit

  • Introduction to Verilog
  • Basic Example
  • Basic Constructs
    • Primitives
    • Signals
    • Operators
    • Constants
  • Procedural Blocks
    • Initial Block
    • Always Block
  • Assignments
  • Hierarchy
  • System Tasks
  • Testbenches in Verilog

Examples edit

Combinational Logic edit

Sequential Logic edit

See Also edit

References edit

  • Digital VLSI Design Lecture 2: Verilog by Adam Teman - 2018
  • Digital Design with an Introduction to Verilog HDL (5th edition)by M. Morris Mano, Michael D. Ciletti