Honeywell 316 (computer)

The Honeywell Series 16 Model 316 was a popular 16-bit minicomputer built by Honeywell starting in 1969.

Honeywell product brochure: *H-316 General Purpose Digital Computer*, November 1969

The Series 16 includes several 16-bit minicomputers: the Model 116, 316, 416, 516 and 716. They were commonly used for data acquisition and control, remote message concentration, clinical laboratory systems and time-sharing. The Series 16 central processors were used to build "Application Systems" which were complete hardware, software and support packages. Standard packages included:

Data Acquisition and Control Systems. Models: 1602, 1603 and 1605
Remote Message Concentrator Systems. Models: 1621 and 1622
Time-Sharing Systems. Models: 1642, 1644, 1646 and 1648A

The data communications systems could be configured as fault-tolerant with dual-processors and a watch-dog timer. The time-sharing systems were multi-processor with a master Control Processor and a slave Job Processor; the larger systems added a dedicated Communication Processor. The processors were tied together via the ICCU (InterComputer Communications Unit.)

There were also ruggedized versions of these processors that were built to military specifications. These models may be identified by an "R" appended to the model number. These included the 316R, 516R and the 1602R. According to a 1971 Summary Description:

"...each system has been tested to ensure its ability to withstand specified levels of punishment."

"Certification came after the computer was shaken, shocked, rocked side to side, frozen, baked, swept to a 10,000 foot altitude, and bombarded with sudden changes in power supply, voltage, and frequency."

One example is that the Model 516R was installed on US Coast Guard ships to gather data for weather forecasting and airborne target tracking.

IMPs, TIPs, and the ARPANET

Front panel of the very first Interface Message Processor, a DDP-516

The company Bolt, Beranek, and Newman (BBN) submitted a proposal to the Advanced Research Projects Agency (ARPA) in 1968 to build "Interface Message Processors for the ARPA Computer Network" in September 1968.

A ruggedized version of the DDP-516 was chosen to build the first generation Interface Message Processor (more commonly known as an "IMP") to connect host computers to the ARPANET. The 516 was originally configured with 12KW of core memory (expandable) and a 16 channel Direct Multiplex Control (DMC) unit. Custom interfaces were used to connect, through the multiplexor, to each of the hosts and modems. In addition to the lamps on the front panel of the 516 there was also a special set of 24 indicator lights to show the status of the IMP communication channels. The IMP performed the function of a store and forward message switcher, the precursor to modern internet routers. Each IMP could support up to four local hosts and could communicate with up to six remote IMPs over 50 Kbps leased lines. Support for 230.4 Kbps circuits was added in 1970.

In 1971 there was a transition to using the non-ruggedized H-316 as an IMP, but it could also be configured as a Terminal IMP (TIP) which added support for up to 63 Teletypes through a multi-line controller. The 316 featured a greater degree of integration than the 516 which made it lighter, less expensive and easier to maintain. The 316 was configured with 20KW of core memory for a TIP. The size of core memory was increased to 16KW for the IMPs and 28KW for TIPs in 1973.

The Honeywell based IMPs were superceded by multiprocessing BBN Pluribus IMPs in 1975. The original IMPs and TIPs were phased out after the introduction of the NSFnet, but some IMPs remained in service as late as 1989.

Miscellany

The H-316 Pedestal Model was also known as the infamous "Kitchen Computer."
"The original Prime computers were compatible with Honeywell Series 16 minicomputers." The early systems software development for the Prime was done on a DDP-516.
Trivia bit - Charles H. (Chuck) Moore "developed the first complete, stand-alone implementation of Forth in 1971" which ran on the DDP-116 and H-316.

History

Honeywell had a long history (1955-1991) of involvement in the computer industry. The company was part of the BUNCH companies competing with IBM in the 1970s. The history is very complex given the number of business mergers and acquisitions in which Honeywell was involved. There were also internal reorganizations that changed the name of the computer division.

These milestones are specific to the Series 16 and related machines, or give general information about Honeywell's computer business. No attempt is made to include mainframes or Multics. The dates given below are best estimates, based on a variety of sources, and the reliability of those sources varies. Additions and corrections are welcome.

Front panel of the H-316

1953 Computer Control Corporation (CCC) founded; CCC was later acquired by Honeywell.
1955 Datamatic Corporation formed; this was a joint venture between: Raytheon Manufacturing Company and the Minneapolis-Honeywell Regulator Company.
1957 Electronic Data Processing (EDP); Honeywell buys out Raytheon's share, and renames Datamatic.
1964 CCC introduces the DDP-116; first 16-bit minicomputer, designed by Gardner Hendrie at CCC.
1965 CCC introduces the DDP-516
1966 Honeywell Computer Control Division; Honeywell buys CCC and forms a division out of it.
1966 Honeywell introduces the DDP-416
1968 The ruggedized DDP-516R chosen for use as ARPA network IMP by BBN.
1969 Honeywell introduces the H-316 and the (renamed) H-516.
1970 Honeywell Information Systems reorganization; Honeywell merges its computer business with General Electric.
1971 H-316 chosen for use as ARPA network TIP and IMP by BBN.
1972 Honeywell introduces the H-716.
1986 Honeywell-Bull formed; Honeywell forms partnership with Compagnie des Machines Bull and NEC.
1989 ARPANET decommisioned, all IMPs and TIPS retired from service.
1991 Honeywell is no longer in the computer business.

Processor registers

The Honeywell minicomputer documented here is a Model 316-01. The processor, core and I/O fit in a single chassis. There is also a second (empty) chassis which could be used for expansion. It was manufactured in 1970, and used in a university electrical engineering department until about 1984.

A basic system included 4kw (16-bit words, w/optional parity) of core memory and could be expanded to 16kw; the optional Extended Addressing module allows up to 32kw. The I/O interfaces are constructed from Honeywell's µ-PACs which are inserted into slots adjacent to the processor backplane. The processor circuit boards are 6.5" by 5" and contain 1/4" flat-pack chips. A Teletype ASR-33 console interface is standard.

Summary of Processing Registers
Register	Function	Mnemonic
Control Registers
Program Counter	16-bit register containing the core address of the next instruction to be executed.	P
Memory Register	16-bit register used to transfer information to and from memory.	M
Address Register	16-bit register containing the location in memory to or from which information is being transferred.	Y
Index Register	16-bit register used in address modification.	X
Arithmetic Registers
Primary Arithmetic Register	16-bit register in which all arithmetic and logical bit manipulation occurs.	A
Secondary Arithmetic Register	16-bit register used in conjunction with A when arithmetic operands exceed one word in length.	B
Overflow Bit	1-bit register used to indicate an overflow status in the arithmetic register.	C
Adder	Logic gating, which performs all arithmetic operations.	-

The instruction set can include extra instructions performed by the (optional) High Speed Arithmetic Unit which adds addition and subtraction that are performed on data in the double-precision format, and hardware multiply and divide.

Instruction Set

Basic Instructions

Data-Handling Instructions

LDA - Load the A Register
STA - Store the A Register
CRA - Clear the A Register
IAB - Interchange A and B
IMA - Interchange Memory and A
INK - Input Keys
OTK - Output Keys
LDX - Load Index Register
STX - Store Index Register

Arithmetic Instructions

ADD - Add
TCA - Twos-Complement of A
ACA - Add Overflow Bit to A
AOA - Add One to A
SUB - Subtract

Logic Instructions

ANA - Logical AND to A
CSA - Copy Sign and Set Sign Plus
CHS - Complement the Sign of A
CMA - Complement the A Register
ERA - Exlusive OR to A
SMM - Set Sign Minus
SSP - Set Sign Plus

Shift Instructions

ALR - Logical Left Rotate
ARR - Logical Right Rotate
ALS - Arithmetic Left Shift
ARS - Arithmetic Right Shift
LGL - Logical Left Shift
LGR - Logical Right Shift
LRS - Long Arithmetic Right Shift
LLS - Long Arithmetic Left Shift
LRL - Long Right Logical Shift
LLL - Long Left Logical Shift
LLR - Long Left Rotate
LRR - Long Right Rotate

Byte-Handling Instructions

CAL - Clear Left Half of A
CAR - Clear Right Half of A
ICA - Interchange Characters in A
ICL - Interchange and Clear Left Half of A
ICR - Interchange and Clear Right Half of A

Control Instructions

CAS - Compare
IRS - Increment, Replace and Skip
ENB - Enable Interrupt
INH - Inhibit Interrupt
HLT - Halt
NOP - No Operation
JMP - Unconditional Jump
JST - Jump and Store Location
RCB - Reset C Bit
SCB - Set C Bit
SKP - Unconditional Skip
SLN - Skip Low-order Bit One
SLZ - Skip if Low-order Bit Zero
SMI - Skip if A Minus
SPL - Skip if A Plus
SNZ - Skip if A Not Zero
SZE - Skip if A Zero
SRn - Skip if Sense Switch #n Reset
SSn - Skip if Sense Switch #n Set
SSC - Skip if C Set
SRC - Skip if C Reset
SSR - Skip if No Sense Switch Set
SSS - Skip if Any Sense Switch Set

Input/Output Instructions

OCP - Output Control Pulse
SKS - Skip if Set
INA - Input to A Register
OTA - Output from A Register
SMK - Set Mask

Featured Capabilities

High-Speed Arithmetic Package

DBL - Enter Double-Precision Mode
SGL - Enter Single-Precision Mode
DLD - Double-Precision Load
DST - Double-Precision Store
DAD - Double-Precision Add
DSB - Double-Precision Subtract
MPY - Multiply
DIV - Divide
NRM - Normalize
SCA - Shift Count to A

Memory Parity Feature

SPN - Skip if No Parity Error
SPS - Skip on Memory Parity Error
RMP - Reset Memory Parity Error

Extended Addressing Feature

EXA - Enable Extended Addressing
DXA - Disable Extended Addressing

Restricted Mode Package

ERM - Enter Restricted Mode

Backplane

Processor backplane configuration
	A
1	CC-374A	ASR Interface
2	CC-365A	Columns A-D
3	CC-365A	Columns A-D
4	CC-370A	M Register
5	CC-371B	Clock
6	CC-364A	Columns 1-4
7	CC-366A	Columns 9-12
8	CC-367	Address Bus
9	CC-372C	Regulator Counter
10	CC-373	Memory Timing
11	CC-401A	High Speed Arithmetic Unit (option)
12	CC-375	High Speed Arithmetic Unit (option)
13	CC-368	Shift Register
14	CC-369B	Lamp Driver
15	N/C	(CC-510A EA/MP option)
16	N/C	(CC-558 MLO/MP option) or (CC-261 if MP option only)
17	CC-079 Cable PAC	Conn 1 CP cable 1	CC-344	Real Time Clock PAC	Cable PAC	Conn 3 MEM
18	CC-080 Cable PAC	Conn 2 CP cable 2	N/C	Conn 8 EA / MP	Cable PAC	Conn 4 MEM
19	N/C	Conn 11 DMC	N/C	Conn 9 EA / MP	N/C	Conn 7 PI
20	N/C	Conn 12 DMC	Cable PAC	Conn 6 I/O	Cable PAC	Conn 5 I/O
	A		B		C

Abbreviations:

N/C - not configured/connected.
CP - Control Panel
DMC - Data Multiplex Control
EA - Extended Addressing
MLO - Memory LockOut
MP - Memory Parity
PI - Priority Interrupt

Configuration

Type No.        Description

316-01          Model 316 computer, 4K memory, rack mountable configuration, includes control panel and power supply
316-02          Additional 4K memory
316-0601        Extended-mode operation for Model 316
316-0602        Expansion package for greater than 16K core
316-0701        Parity for first 4K of core
316-0702        Parity for each additional 4K of core
316-0800        Base sector relocation
316-0801        Memory lockout for first 8K of core
316-0802        Memory lockout for each additional 8K of core
316-11          High-speed arithmetic package
316-12          Real-time clock
316-20          Direct multiplex control (DMC) unit, controls 16 devices
316-21          High-speed DMC, controls 16 devices
316-25          Group of four priority interrupt lines
316-25-1        Additional group of four priority interrupt lines
316-26          Memory counter modification for group of four priority interrupt lines
316-29          16 SKS and 16 OCP lines

External links

Adrian Wise's Honeywell Series 16 website] (Includes a Series 16 emulator.)
Bob Supnik's Computer History Simulation Project (Includes an H-316 emulator and a paper on the "Generic A" Instructions.)
Ed Thelen's DDP-116, CCD-516, H-316
Honeywell DDP-516 (at the old-computers.com website.)

References

The ARPANET Interface Message Processor (IMP) Port Expander (PE) SRI International, November, 1980. (PDF format)