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Computer Architecture Lab/WS2008

Gruppe 0Edit

Matthias Feurstein

IS1Edit

Vergleich der Instruktionssets von:

  1. Z80
  2. Atmel AVR
  3. ARM7TDMI

Vergleich:


Gruppe 1Edit

Sweet 16 (Gruppe 2)Edit

Franz-Josef Katzdobler, Daniel Reichhard, Stefan Resch, Matthias Wenzl

Instruction Set IEdit

The discussion and the comparison of the instruction sets from

can be found here.

Documentation

Gruppe 3Edit

Christian Pfeifhofer, Michael Wessner, Michael Zoech

Instruction Set 1Edit

Comparison of the instruction sets of:

  1. PICMicro PIC16Cxxx
  2. DEC Alpha
  3. Intel 4004

Instruction Set 2Edit

The instruction set of our processor:

Processor DocumentationEdit

The documentation of our processor is available in pdf format:

AUA (Another Useless Architecture)Edit

  • Rottensteiner Stefan
  • Tauner Stefan
  • Wilhelm Jakob

Instruction Set ComparisonEdit

  • AVR32
  • Intel i960
  • SuperH

Our own CPUEdit

A quite standard 16bit RISC implementation with 32 registers and probably a 4 stage pipeline (ex and mem combined).

AUA

Gruppe 5 (Project: MaQuelle)Edit

Instruction Set IEdit

  • Infineon TriCore
  • Freescale MPC7448 (PowerPC)
  • Motorola 68000

Comparison: