Diogenes Instruction SetEdit
(Minimalistic Instruction Set Architecture)
Diogenes is a 32 Bit reduced RISC with 16 Bit wide instructions. It uses 16 general purpose registers, each 32 Bit wide.
There are several Types of Instructions:
- Arithmetic and Logic (3 Registers)
- Load Immediate (1 Register, 8Bit Immediate)
- Compare (3 Registers)
- Branch (1 Register condition, 8Bit signed Offset)
- Add/shift (1 Register, 6Bit Immediate)
- unconditional Jump (2 Registers: jump address and saved PC for calls)
- Move (2 Registers)
- Load/store (2 Registers, and
- select (special instructions for selecting (sign-extended) bytes or halfwords of a 32-Bit word)
- The 16 registers of diogenes are named l0 to l7 and h0 to h7.
- Most instructions may use all registers arbitrary as destination- and source-registers.
Two registers with the same number (e.g. l3 and h3) are called "brother-registers".
Some instructions may only use the first source-register or its corresponding brother-register as the result-register (e.g. "adi r1, r1, 1", and "adi r1, h1, 5" are allowed while "adi r1, r2, 1" is not possible).
Detailed Instruction Set and Bit encodingEdit
The most significant bits of the instruction word define the instruction category.
|add||rd = ra + rb|
|subtract||rd = ra - rb|
|logical bitwise and||rd = ra + rb|
|logical bitwise or||rd = ra or rb|
|logical bitwise xor||rd = ra ^ rb|
|shift left signed||rd = ra << rb||rb is interpreted as signed value, negative values indicate an arithmetic shift right|
Load Immediate InstructionsEdit
|load 8bit||rd = imm|
|shift and load 8bit||rd = (rd << 8) + imm|
These 8-Bit instructions can be used to load immediate values. For example to load the 32 Bit Value 0x87654321 to r1, the following instructions can be executed:
- ldi r1, 0x87
- shi r1, 0x65
- shi r1, 0x43
- shi r1, 0x21
Our assembler supports a pseudo instruction to load 32-Bit values and uses these instructions internally.
Compare instructions compare the values of the registers ra and rb (that might be any of the 16 general purpose registers) and writes 0 or zero to the chosen register rd. The compare operations available are ra < rb for both signed and unsigned numbers. The semantic of >, <= or >= can be modeled with the branch instructions and/or exchanging ra and rb.
In this category, two instructions are still undefined, and might be used for future extensions like like multiplication.
Branch instructions are PC-relative (Program Counter) and have an 8 Bit signed offset. The check the contents of an register an branch either on a zero or non-zero value of this register. In the decode-stage (stage 2) the branch gets active and thus has one delayslot.
shift/add 6Bit Immediate InstructionsEdit
These instructions are used to add or shift the value of a register with a 6Bit signed Immediate value. The result is stored in rd while the source-register may either be rd or the brother-register of rd.
- The jump instruction unconditionally jumps to the address stored in ra with one delay slot (note that rd is ignored by this instruction and should be 0 to enable future extensions).
- The call instruction is exactly the same as jump, except that the value of PC is stored to rd before the jump.
- The move instruction simply moves the contents of ra to rd
- The ld/ldio instructions load a value from address ra to rd (from internal memory resp. I/O).
- The st/stio instructions store the value of rd to a location at address ra (in internal memory resp. I/O). Note that this instruction does not use rd as destination-register.
Select Instructions (currently not implemented)Edit
Select instructions are used to mask out a signed or unsigned, word or halfword from a 32 bit register. They can be used to "emulate" unaligned memory access (which is not supported by ld/st instructions) and to sign/zero extend byte and halfword values.
- the seh and seb instructions use the lower bits of register ra to determin which byte or halfword should be selected. They treat values as unsigned.
- the seixx intructions select the byte/halfword specified by imm and are available in signed and unsigned versions.
- these instructions are not implemented in our current processor design (and might be removed).