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Computer Architecture Lab/WS2007/ZoWeAySi/Instruction Set II

Instruction Set IIEdit

FeaturesEdit

  • 32-bit RISC processor
  • Load/Store architecture
  • Harvard architecture
  • 32 32-bit general purpose registers
  • 32-bit instruction width
  • 4 pipeline stages
  • memory mapped IO

RegistersEdit

GP RegistersEdit

Our Processor has 32 GP registers:

  • $0 always zero
  • $1..30 arbitrary
  • $31 Stack Pointer

FlagsEdit

Our Processor features 4 flags in the flag register:

  • CF .. Carry Flag
  • SF .. Sign Flag
  • ZF .. Zero Flag
  • OF .. Overflow Flag

Instruction EncodingEdit

Instruction FormatsEdit

R-Type:

Opcode rt rd rs cc unused
6Bit 5Bit 5Bit 5Bit 4Bit 7Bit

I-Type:


Opcode cc/rt rd immediate
6Bit 5Bit 5Bit 16Bit

Conditions (cc)Edit

Encoding Condition cc Description
0000 (unused) none unused at I-Type, LSB(rt) at R-Type
0001  ZF NZ, NE if ZF is not set, if not Equal
0010  SF NS if SF is not set
0011  OF NO if OF is not set
0100  CF NC, AE if CF is not set, if Above or Equal (unsigned)
0101  (CF   ZF) A if Above (unsigned)
0110  (SF   OF) GE if Greater than or Equal (signed)
0111  ((SF   OF)   ZF) GT if Greater than (signed)
1000 true none true at I-Type, MSB(rt) at R-Type
1001 ZF ZF, EQ if ZF is set, if Equal
1010 SF SF if SF is set
1011 OF OF if OF is set
1100 CF CF, B if CF is set, if Below (unsigned)
1101 CF   ZF BE if Below or Equal (unsigned)
1110 SF   OF LT if Less Than (signed)
1111 (SF   OF)   ZF LE if Less than or Equal (signed)

Processor InstructionsEdit

R-TypeEdit

Instruction Semantics Flags Opcode rt rd rs cc Description
ADD rd rs rt rd := rs + rt ZF, SF, OF, CF 000000 rt rd rs 0000 Add
SUB rd rs rt rd := rs - rt ZF, SF, OF, CF 000001 rt rd rs 0000 Subtract
ADC rd rs rt rd := rs + rt + CF ZF, SF, OF, CF 000010 rt rd rs 0000 Add with carry
SBB rd rs rt rd := rs - rt - CF ZF, SF, OF, CF 000011 rt rd rs 0000 Subtract with borrow
INSccL rd rs rd := (rs<<1)+ cc ZF, SF, OF, CF 000100 rs rd rs cc Insert condition low
INSLL rd rs rt rd := (rs<<1)+ LSB(rt) ZF, SF, OF, CF 000100 rt rd rs 0000 Insert LSB low
INSML rd rs rt rd := (rs<<1)+ MSB(rt) ZF, SF, OF, CF 000100 rt rd rs 1000 Insert MSB low
INSccH rd rs rd := (rs>>1)+cc*2^31 ZF, SF, OF, CF 000110 $0 rd rs cc Insert condition high
INSLH rd rs rt rd := (rs>>1)+LSB(rt)2^31 ZF, SF, OF, CF 000110 rt rd rs 0000 Insert LSB high
INSMH rd rs rt rd := (rs>>1)+MSB(rt)2^31 ZF, SF, OF, CF 000110 rt rd rs 1000 Insert MSB high
AND rd rs rt rd := rs   rt ZF, SF 001000 rt rd rs 0000 And
ANDN rd rs rt rd := rs    rt ZF, SF 001001 rt rd rs 0000 And Not
XOR rd rs rt rd := rs   rt ZF, SF 001010 rt rd rs 0000 Xor
XORN rd rs rt rd := rs    rt ZF, SF 001011 rt rd rs 0000 Xor Not
OR rd rs rt rd := rs   rt ZF, SF 001100 rt rd rs 0000 Or
ORN rd rs rt rd := rs    rt ZF, SF 001101 rt rd rs 0000 Or Not
LD rd rt rd := [rt] none 010000 rt rd $0 0000 Load from Address
ST rt rs [rt] := rs none 010010 rt $0 rs 0000 Store to Address
MOVcc rd rs rt rd := (cc)? rs: rt none 010100 rt rd rs cc Move on Condition
JMP rs pc := rs none 011100 01000 $0 rs 0000 Jump indirect
Jcc rs pc := (cc)? rs: pc+4 none 011100 cc $0 rs 0000 Jump indirect if cc
JSR rs [sp]:=pc+4; pc:=rs none 011110 sp $0 rs 0000 Jump to Subroutine indirect

I-TypeEdit

Instruction Semantics Flags Opcode rt/cc rd imm Description
IADD rd imm rt rd := imm + rt ZF, SF, OF, CF 100000 rt rd imm Immediate Add
ISUB rd imm rt rd := imm - rt ZF, SF, OF, CF 100001 rt rd imm Immediate Subtract
IADC rd imm rt rd := imm + rt + CF ZF, SF, OF, CF 100010 rt rd imm Immediate Add with carry
ISBB rd imm rt rd := imm - rt - CF ZF, SF, OF, CF 100011 rt rd imm Immediate Subtract with borrow
IAND rd imm rt rd := imm   rt ZF, SF 101000 rt rd imm Immediate And
IANDN rd imm rt rd := imm    rt ZF, SF 101001 rt rd imm Immediate And Not
IXOR rd imm rt rd := imm   rt ZF, SF 101010 rt rd imm Immediate Xor
IXORN rd imm rt rd := imm    rt ZF, SF 101011 rt rd imm Immediate Xor Not
IOR rd imm rt rd := imm   rt ZF, SF 101100 rt rd imm Immediate Or
IORN rd imm rt rd := imm    rt ZF, SF 101101 rt rd imm Immediate Or Not
LDI rd imm rd := [imm] none 110000 $0 rd imm Load from immediate Address
STI imm rt [imm] := rt none 110010 rt $0 imm Store to immediate Address
INSI rd imm rt rd := imm + (rt << 16) none 110100 rt rd imm Insert immediate into register
INSIN rd imm rt rd := imm + (~rt << 16) none 110101 rt rd imm Insert immediate into negated register
RET imm pc := [sp]; sp += imm none 111000 sp sp imm Return (and clean up stack)
JMP label pc := label none 111100 01000 $0 label Jump to target address
JMPcc label pc := (cc)? label: pc+4 none 111100 cc $0 label Jump to target address if cc
JSR label [sp]:=pc+4; pc:=label none 111110 sp $0 label Jump to Subroutine

Instruction MappingsEdit

Instruction Semantics Flags Mapping
CMP rs rt rs - rt ZF, SF, OF, CF SUB $0 rs rt
CMPI rt imm rt - imm ZF, SF, OF, CF IADD $0 -imm rt
ICMP imm rt imm - rt ZF, SF, OF, CF ISUB $0 imm rt
MOV rd rs rd := rs none MOVCF rd rs rs
NEG rd rt rd := -rt ZF, SF, OF, CF SUB rd $0 rt
NOP none MOVCF $1, $1, $1
NOT rd rs rd :=  rs ZF, SF XORN rd rs $0
RCL rd rs ZF, SF, OF, CF ADC rd rs rs
RCR rd rs ZF, SF, OF, CF INSCFH rd rs
RET pc := [sp]; sp += 4; none RET 4
ROL rd rs ZF, SF, OF, CF INSML rd rs rs
ROR rd rs ZF, SF, OF, CF INSLH rd rs rs
SAR rd rs rd := rs >>> 1 ZF, SF, OF, CF INSMH rd rs rs
SETcc rd rd := (cc)? 1: 0 ZF, SF, OF, CF INSccL rd $0
SHL rd rs rd := rs << 1 ZF, SF, OF, CF ADD rd rs rs
SHR rd rs rd := rs >> 1 ZF, SF, OF, CF INSMH rd rs $0
SUBI rd rt imm rd := rs - imm ZF, SF, OF, CF IADD rd -imm rt