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Three Micro Discussion

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PIC18F2455

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Overview

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  • Harvard Architecture (data and program memory use seperate busses)
  • RISC Architecture (75 standard instructions)
  • 8-bit ALU with single Accumulator (WREG)
  • 24Kbytes flash memory to store up to 12288 single-word instructions
  • 2Kbytes SRAM
  • 256 bytes EEPROM
  • 24 I/O pins
  • Support interrupt priority
  • USB Serial Interface Engine
  • USART, A/D, Capture/Compare/PWM, Timers, SPI, I2C
  • Hardware Stack (31)

Memory Organization

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Program Memory
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The PIC18F microcontroller has 24Kbytes of flash memory for program storage and is divided into two sections, the boot and the application program section. The Program Counter (PC) is 21 bits wide, and accesses bytes in the program memory. Since all instructions are either 16 or 32 bits wide the least significant bit of the PC is always zero.

The microcontroller features several interrupt sources and two interrupt priority levels.

  • Reset Vector at address 0x0000h
  • High Priority Interrupt Vector at address 0x0008h
  • Low Priority Interrupt Vector at address 0x0018h
Data Memory
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The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). SFRs are used by the CPU and peripheral modules for control and status of the controller and peripheral functions. GPRs are used for data storage.

The data memory space is divided into 16 banks, each bank with a size of 256 bytes. Any memory location can be addressed either by its address (12 bits) or an low-order address and a 4-bit bank pointer (BSR). When accessing memory registers the 8-bit low-order address is part of the instruction. To ensure fast access of SFRs and the first 96 bytes of Bank 0 the PIC18F device contains an Access Bank with a total size of 256 bytes. This Bank can be accessed only with a 8-bit address. One bit inside instructions, is used to determine either the Access Bank or the GPR Banks.

The PIC18F2455 supports direct, indirect or indexed Addressing modes.

Instruction Set Summary

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The PIC18F controller has a set of 75 standard instructions, as well as an extended set of eight instructions. The extended instruction set is disabled by default and can enabled through device configuration bits.

The Standard Instruction Set is grouped into four categories:

  • Byte-oriented operations
  • Bit-oriented operations
  • Literal operations
  • Control operations
Byte-oriented Operations
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Most byte-oriented operations have 3 operands.

'd' is zero => result is placed in WREG.

'd' is one => result is placed in 'f'

'a' is zero => BSR (Bank Select Register) is ignored and the Access Bank is used

'a' is one => RAM Bank is specified by BSR

'f' 8-bit register file address


Bit 15:10 Bit 9 Bit 8 Bit 7:0
OPCODE d a f(FILE #)
e.g, ADDWF MYREG, W, B (Add WREG and f)
Bit-oriented Operations
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Bit-oriented operations have 3 operands

'b' 3-bits to select one bit of 'f'

'a' is zero => BSR is ignored and the Access Bank is used

'a' is one => RAM Bank is specified by BSR

'f' 8-bit register file address


Bit 15:12 Bit 11:9 Bit 8 Bit 7:0
OPCODE b(BIT #) a f(FILE #)
e.g., BSF MYREG, bit, B (Bit set f)
Literal Operations
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Literal operations have only one operand

'k' 8-bit immediate value


Bit 15:8 Bit 7:0
OPCODE k (literal)
e.g., MOVLW 7Fh (move literal to WREG)
Control Operations
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'n' 20-bits immediate value


Bit 15:8 Bit 7:0
OPCODE n<7:0> (literal)


Bit 15:12 Bit 11:0
1111 n<19:8> (literal)
e.g., GOTO Label (Goto Address)

Pipeline

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The clock input is internally divided by four to generate four non-overlapping quadrature clocks. Each instruction cycle consists of such four quadrature clocks.

Two Stage pipeline

  • Instruction fetch
  • Instruction decode and execute

PIC Tutorials

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INTEL 8086

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Overview

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  • Direct addressing capability: 1 MB of memory
  • 20 bits addressing
  • Architecture designed for Assembly Language
  • 14 Word, by 16-bit register set
  • 24 Operand addressing modes
  • Bit, byte, word and block operations
  • 8 and 16-bit signed and unsigned arithmetic in binary or decimal including multiply and divide

Memory Organization

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  • Linear array of up to 1 million bytes
  • Logically divided into code, data, extra data and stack segments of up to 64K bytes each
  • Memory references relative to base addresses contained in high speed segment registers
  • Little Endian
  • Physically: high bank (D15 – D8) and low bank (D7 – D0) of 512K 8-bit bytes addressed in parallel by the processor’s address lines
  • Certain locations are reserved for specific CPU operations

Instruction Set Summary

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Data Transfer
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The MOV instruction is used to transfer 8 and 16-bit data to and from registers. Either the source or destination has to be a register. The other operand can come from another register, from memory, from immediate data (a value included in the instruction) or from a memory location “pointed at” by register BX.

I/O Operations
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The 8086 has separate I/O and memory address spaces. Values in the I/O space are accessed with IN and OUT instructions. The port address is loaded into DX and the data is read/written to/from AL or AX.

Arithmetic/Logic
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Arithmetic and logic instructions can be performed on byte and 16-bit values. The first operand has to be a register and the result is stored in that register.

Control Transfer
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Conditional jumps transfer control to another address depending on the values of the flags in the flag register. Conditional jumps are restricted to a range of -128 to +127 bytes from the next instruction while unconditional jumps can be to any point.

  • The CALL and RET instructions call and return from subroutines. The processor pushes IP on the stack during a CALL instruction and the contents of IP are popped by the RET instructions.


Pipeline

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Fetch/Execute:

Tasks are divided into 2 sections: Fetch (BIU), and Execute (EU). Different circuits for every function, but working in parallel. At the beginning, just Fetch can waste time. From then and on, Fetch goes first than Execute, bringing instructions to the processor, while this one is executing those were brought in advance.


OR1200 CPU

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OR1200 is intended for embedded, portable and networking applications. It can successfully compete with latest scalar 32-bit RISC processors in his class and can efficiently run any modern operating system.

The OR1200 CPU/DSP is a central part of the OR1200 RISC processor. It is a RISC CPU with Harvard microarchitecture, a 5-stage pipeline and with a virtual memory support (MMU) and with basic DSP capabilities. It was developed in the OpenRisk project. The whole hardver is open, all major characteristics of the core can be set by the user. It has separated instruction and separated data memory management.

References

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OpenRISC 1200 IP Core Specification: Damjan Lampret

Cache

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The default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged. Instruction/data cache size scalable from 1KB to 64KB.

I/O

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It has no separate Input/Out Unit. It has Memory mapped I/O.

Registers

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OpenRISC 1200 implements 32 general-purpose 32-bit registers. OpenRISC 1000 architecture also support shadow copies of register file to implement fast switching between working contexts, however this feature is not implemented in current OR1200 implementation. OR1200 implements general-purpose register file as two synchronous dual-port memories with capacity of 32 words by 32 bits per word.


Pipeline

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Scalar, single-issue 5-stage pipeline delivering sustained throughput.

Interrupts

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It has 2 non-maskable, 30 maskable interrupt sources, and two interrupt priorities level. The Interrupts are used for the Task-Scheduling. It is called Programmable Interrupt Controller (PIC).

Instruction Set

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The instruction unit implements the basic instruction pipeline, fetches instructions from the memory subsystem, dispatches them to available execution units, and maintains a state history to ensure a precise exception model and that operations finish in order. It also executes conditional branch and unconditional jump instructions. The instruction set is grouped into the Program Control Group, Logical Group, Arithemtic Group, Shift and Rotate Group, Input/Output Group and Interrupt Group. In total the processor supports 3 operands instructions. The most instructions execute in 1 clock cycles. The istruction set is the standard ORBIS32 type. The ORFPX32/64 and ORVDX64 instruction classes are not supported by current OR1200.

Our Processor's Instruction Set

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General Features

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These are the main characteristics of our microprocessor that have been taken into consideration before "creating" the instruction set:

  • Data and program separate memories
  • 16 16-bit general purpose registers (GPR)
  • Register - register addressing mode (some special immediate and indirect addressing mode instructions)
  • 16-bit status register
  • 128 Kbytes data memory and 128 Kbytes program memory
  • Numerical data can be expressed in decimal, hexadecimal (h after the number) or binary (b after the number).

INSTRUCTIONS

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Complete set (Opcodes 0101 and 1011 are still free):

  • Arithmetic: ADD, SUB, ADDI, SUBI.
  • Logical: AND, OR, NOT, SHFL, SHFR.
  • Special: MOV, MOVUI, MOVLI, NOP.
  • Conditional branches: BEQ, BNEQ, SLT, SLTI.
  • Unconditional branch: J, JAL, RET.
  • Data transfers: LD, ST, LDI, STI.


Arithmetic

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These instructions rise the zero, carry and negative flags when it proceeds.

  • ADD, SUB


Bit 15:12 Bit 11:8 Bit 7:4 Bit 3:0
OPCODE Op1 Op2 Func

Where OPCODE=0001 and Func=0000(ADD) or 0001(SUB). Op1 is source and destination register while Op2 is only source register (both GPR)

e.g., ADD R1, R8 

                  R1 ← R1+R8

SUB R1, R8 

                  R1 ← R1-R8


  • ADDI


Bit 15:12 Bit 11:8 Bit 7:0
OPCODE Op1 Op2 (DATA)

Where OPCODE=0010. Op1 is source and destination register while Op2 is an immediate addressed source data of 8 bits maximum.

e.g., ADDI R3, F2h 

                  R3 ← R1+11110010


  • SUBI


Bit 15:12 Bit 11:8 Bit 7:0
OPCODE Op1 Op2 (DATA)

Where OPCODE=0100. Op1 is source and destination register while Op2 is an immediate addressed source data of 8 bits maximum.

e.g., SUBI R3, F2h 

                  R3 ← R1-11110010

Logical

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  • AND, OR, NOT, SHFL, SHFR


Bit 15:12 Bit 11:8 Bit 7:4 Bit 3:0
OPCODE Op1 Op2 Func

Where OPCODE=0011 and Func=0010(AND), 0011(OR), 0100(NOT), 0101(SHFL) or 0110(SHFR). Op1 is source and destination register while Op2 is only source register (both GPR) in the instructions AND and OR. In the instructions NOT, SHFL and SHFR Op1 is only destination register. AND and OR can rise the zero flag (ZF) while SHFL and SHFR can rise the overflow flag (OF).

e.g., AND R2, R4 

               R2 ← R2 AND R4 (bit by bit)

OR R2, R4 

               R2 ← R2 OR R4 (bit by bit)

NOT R2, R4 

               R2 ← NOT R4 (bit by bit)

SHFL R2, R4 

               R2 << #R4  (filling with zeroes)

SHFR R2, R4 

               R2 >> #R4 (filling with zeroes)

Special

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  • MOV


Bit 15:12 Bit 11:8 Bit 7:4 Bit 3:0
OPCODE Op1 Op2 Func

Where OPCODE=0001 and Func=0111 Op1 is destination register while Op2 is source register (both GPR).

e.g., MOV R9, R5 

               R9 ← R5


  • MOVUI


Bit 15:12 Bit 11:8 Bit 7:0
OPCODE Op1 Op2 (DATA)

Where OPCODE=0110. Op1 is destination (only its 15-8 bits) register while Op2 is an immediate addressed source data of 8 bits maximum.

e.g., MOVUI R9, 00101110b 

               R9(15-8) ← 00101110


  • MOVLI


Bit 15:12 Bit 11:8 Bit 7:0
OPCODE Op1 Op2 (DATA)

Where OPCODE=0111. Op1 is destination (only its 7-0 bits) register while Op2 is an immediate addressed source data of 8 bits maximum.

e.g., MOVLI R9, 00101110b 

               R9(7-0) ← 00101110


  • NOP


Bit 15:0
0000000000000000

NO OPERATION

Conditional branches

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  • BEQ, BNEQ


Bit 15:12 Bit 11:10 Bit 9:0
OPCODE Flag Relative jump

Where OPCODE=1000(BEQ) or 1001(BNEQ). The jump will take place depending on the value at the specified flag of the Status Register. The relative jump cannot be greater than 10 bits. If it were, the assembler would print an error message.

e.g., BEQ ZF, 1001101001b 

                  if (ZF = 1) then PC ← PC + 1001101001

BNEQ ZF, label1 

                  if (ZF = 0) then PC ← label1


  • SLT


Bit 15:12 Bit 11:8 Bit 7:4 Bit 3:0
OPCODE Op1 Op2 Func

Where OPCODE=0001 and Func=1100. Op1 and Op2 are both source general purpose registers. If Op1 is smaller than Op2 then a flag will be activated in the Status Register.

e.g., SLT R1, R8 

                  if (R1 < R8) then NF=1


  • SLTI


Bit 15:12 Bit 11:8 Bit 7:0
OPCODE Op1 Op2 (DATA)

Where OPCODE=1100. Op1 is a general purpose register while Op2 is an immediate addressed source data of 8 bits maximum.. In this instruction, in case Op1<Op2 then the negative flag (NF)will be activated in the Status Register.

e.g., SLTI R1, d12 

                  if (R1(bits 7:0)=00001100) then NF=1

Unconditional branch

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  • J


Bit 15:12 Bit 11:0
OPCODE Absolute Address

Where OPCODE=1101. The absolute address can be both specified by the PC value or a label.

e.g., J label1 

                  PC ← label1

J F0Bh 

                  PC ← 111100001011


  • J (the same name but slightly different working way)


Bit 15:12 Bit 11:8 Bit 7:4 Bit 3:0
OPCODE Indirect Address 0000 Func

Where OPCODE=0001 and Func=1000.

e.g., J (R3) 

                  PC ← (R3)


  • JAL


Bit 15:12 Bit 11:8 Bit 7:4 Bit 3:0
OPCODE Op1 0000 Func

Where OPCODE=0001, Func=1001 and the next program counter is changed to the value in R1. The former program counter + 2 will be kept into a general purpose register. When using a label the assembler generates a pseudo-instruction.

e.g., JAL R3 

               R3 ← PC + 2; PC ← R1

PSEUDO-INSTRUCTION!!! JAL R3, label2 

               MOVIU R1, label2[15:8]; MOVIL R1, label2[7:0]; JAL R3


  • RET


Bit 15:12 Bit 11:8 Bit 7:0
OPCODE Op1 00000000

Where OPCODE=0011. Return from a subroutine and PC takes the value in the specified register.

e.g., RET R3 

               PC ← R3

Data transfers

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  • LD, ST


Bit 15:12 Bit 11:8 Bit 7:4 Bit 3:0
OPCODE Op1 Op2 Func

Where OPCODE=0001 and Func=1010(LD) or 1011(ST). Op1 is destination while Op2 is source. LD moves a data from memory to a register and ST does the opposite. In both instructions, one of the operands is specified by using indirect addressing mode.

e.g., LD R9, (R5) 

               R9 ← (R5)

ST (R9), R5 

               (R9) ← R5


  • LDI


Bit 15:12 Bit 11:10 Bit 9:0
OPCODE Op1 Op2 (DATA)

Where OPCODE=0011. Op1 designs a general purpose register among R12, R13, R14 and R15 while Op2 is an immediate addressed source data of 10 bits maximum.


e.g., LDI (R14), 0011001100b 

               R14 ← (0011001100)


  • STI


Bit 15:12 Bit 11:10 Bit 9:0
OPCODE Op1 Op2 (DATA)

Where OPCODE=0101. Op2 designs a general purpose register among R12, R13, R14 and R15 while Op2 is an immediate addressed source data of 10 bits maximum.


e.g., STI (0011001100b), R14 

               (0011001100) ← R14
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