Wikiversity

Computer Architecture Lab/Summer2006/CzinkPokornyResch/VRIPU

< Computer Architecture Lab | Summer2006

This is the project page for VRIPU (Very Reduced Instructions Processing Unit) microprocessor.

Short description

edit

The goal of the VRIPU project is to design a pipelined RISC microprocessor which will only have a few instructions (about twenty).

VRIPU Datasheet

edit

The datasheet for VRIPU can be found here.

Retrieved from "https://en.wikiversity.org/w/index.php?title=Computer_Architecture_Lab/Summer2006/CzinkPokornyResch/VRIPU&oldid=2145996"