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Computer Architecture Lab/Summer2006/CzinkPokornyResch/VRIPU

< Computer Architecture Lab‎ | Summer2006

This is the project page for VRIPU (Very Reduced Instructions Processing Unit) microprocessor.

Short description

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The goal of the VRIPU project is to design a pipelined RISC microprocessor which will only have a few instructions (about twenty).

VRIPU Datasheet

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The datasheet for VRIPU can be found here.

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