Computer Architecture Lab/SS2014/group 4 lab 1

AVR

AVR (not to be confused with AVR32) is an 8-bit microcontroller architecture by ATMEL ^[1]. It'a modified Harvard architecture RISC single chip microcontroller ^[2] with instructions of both 16- and 32-bits. On most implementations most operations (excluding memory ops.) are single cycle. The instruction set includes many opcode formats. This makes it difficult to pipeline it further than the two stages atmel uses in their implementations ^[3] (fetch and execute). This significantly limits the speed and therefor thourghput of the AVR. Max speed for commercial is 32MHz for the XMEGA.

AVR is mostly used on low power/low cost processors. Such as the popular ATtiny.

Features

Load/store architecture, all instructions work on registers only. Some instructions may, however, work on pairs of registers at once (instructions for 16-bit arthritics)
32 general purpose registers.
64 (256 on specific chips) I/O registers used for I/O, stack pointer, and some special registers that can be concatenated with X,Y or Z for addressing on MCUs with more than 64K memory. I/O registers are placed in data memory, but the first 64 of them can be accessed more quickly.
Separate data and program memory. Data memory is addressed in 8-bit blocks, program in 16-bit blocks.
Special instructions for read/write to/from program memory. Enables string constants, boot-loaders etc.
Mostly fixed instruction length of 16-bit, but some requires an extra 16-bit block.
Special status register for comparison, global interrupt enabling and a special instruction.

Registers

The architecture features 32 general purpose registers, of which three can be used in pairs as 16-bit registers. These are X = R27:26, Y = R29:R28, Z = R31:R30. Furthermore 64 (256 on chips with extended I/O registers) I/O registers used for I/O (both physical I/O and accessing peripherals - such as hardware PWM, UART, memory protection etc.), stack pointer, and some special registers that can be concatenated with X,Y or Z for addressing on MCUs with more than 64K memory. I/O registers are placed in data memory, but the first 64 of them can be accessed more quickly.

The 8-bit status register has the following bits:

C: Carry Flag
Z: Zero Flag
N: Negative Flag
V: Two’s complement overflow indicator
S: N ⊕ V, For signed tests
H: Half Carry Flag
T: Transfer bit used by BLD and BST instructions
I: Global Interrupt Enable/Disable Flag

Registers are the first 32 bits of the data memory, and can also be addressed as such. I/O is the next 64 or 256 bits of data memory. General data memory starts after that.

Opcode formats/addressing modes

15	11	10	09	05	04
Register Direct, Single Register Rd
OP					Rd → Register File
Register Direct, Two Registers Rd and Rr
OP			Rr → Register File		Rd → Register File
I/O Direct
OP		Rr/Rd → Register File		A → I/O Memory
Data Direct
OP					Rr/Rd → Register File
Data Address → Data Space
Data Indirect with Displacement
OP		Rr/Rd → Register File		q (+ Y or Z) → Data Space
Data Indirect
(X, Y or Z) → Data Space
Data Indirect with Pre-decrement after instruction X, Y or Z is decreased by 1
(X, Y or Z) - 1 → Data Space
Program Memory Constant Addressing using the LPM, ELPM, and SPM Instructions
Z → Program Memory (LSB of Z chooses first or last 8-bit of the 16-bit line)
Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction Z is incremented after this
Z + 1 → Program Memory (LSB of Z chooses first or last 8-bit of the 16-bit line)
Direct Program Addressing, JMP and CALL
OP				6 MSB → 6 MSB of PC
16 LSB → 16 LSB of PC
Indirect Program Addressing, IJMP and ICALL
Z → PC
Relative Program Addressing, RJMP and RCALL k is 2's comp.
OP	k ( + PC ) + 1 → PC

Instruction-set

The instruction-set is modified Harvard architecture 8-bit RISC. Instructions are 16-bit, though some instructions take an extra line of program memory, thus becoming 32-bit ex: CALL

Complete instruction set is found at Atmel AVR datasheet page 11, A more comprehensive list can be found at Instruction_list

None-unique instructions

No all instructions are unique. Some instructions are replaced by the assembler with other instructinos, performing the same operation. ex: the clear register CLR will be replaced by an instruction to perform a bitwise xor operation with the register itself.

ARMv7

ARMv7 is an instruction set architecture created by ARM holdings. It is the current installment of the extremely successful ARM architectures and is used in most embedded applications using 32-bit processors. It is especially popular in the mobile phone market. Apple, Samsung, Qualcomm and Broadcom all have processors implementing the ARMv7 architecture. As it is a huge architecture, this is only a general view.

Features

Load/store architecture
32 bit words
16 useable 32-bit registers
Fixed instruction length of one word
Conditional execution of single operations
Dedicated link register.
Banked registers for interrupts.
2^32 byte addressed flat memory space.
Bit shift operations can be executed in the same cycle as arithmetic/move/logic operations.
Configurable endianness.
SIMD support.
Can execute 3 instruction sets, ARMv7, Thumb and Thumb-2.

Registers

There are 16 programmer accessible registers of which 13 are general purpose, R0 through R12. R13 through R15 are special registers. R13 contains the stack pointer, R14 contains the return address of a subroutine call and R15 contains the program counter. When an interrupt occurs, the processor mode is changed to that of the specific interrupt that occured. Each of these modes have unique versions of R13 and R14.

Additionally a CPSR register is available. This special purpose register holds information about the processor state. It has the following layout ^[4]

M (bits 0–4) is the processor mode bits.
T (bit 5) is the Thumb state bit.
F (bit 6) is the FIQ disable bit.
I (bit 7) is the IRQ disable bit.
A (bit 8) is the imprecise data abort disable bit.
E (bit 9) is the data endianness bit.
IT (bits 10–15 and 25–26) is the if-then state bits.
GE (bits 16–19) is the greater-than-or-equal-to bits.
DNM (bits 20–23) is the do not modify bits.
J (bit 24) is the Java state bit.
Q (bit 27) is the sticky overflow bit.
V (bit 28) is the overflow bit.
C (bit 29) is the carry/borrow/extend bit.
Z (bit 30) is the zero bit.
N (bit 31) is the negative/less than bit.

Every instruction is executed depending of the value of the VCZN fields.

Addressing modes

For arithmetic/logic operations

Register
Immediate

For load operations

Register indirect
Displacement
Indexed
Autoincrement/decrement, pre and post load
Scaled

Instruction sets

As well as executing normal ARM instructions, a 16 bit wide subset of ARM instructions called Thumb and a mixed 16/32 bit instruction set named Thumb-2 can also be executed on ARMv7 architectures. The instruction set being executed is specified in the CSPR register.

An overview of the several instruction formats can be found here: http://cseweb.ucsd.edu/~kastner/cse30/arm-instructionset.pdf

TI msp430

The Texas Instruments MSP430 is a 16-bit, low-cost, low-power chip family and architecture.

Registers

16 registers of which R0 is PC, R1 is stack pointer, R2 is status register/constant generator 1, R3 is constant generator 2 and R4-15 is general purposes. The status register has the following fields: C carry bit, V overflow bit, N negative bit, Z zero bit.

Addressing modes

Instructions are accumulator types, where the destination is also a source register

The msp320 has a quite sophisticated addressing scheme - for all instructions the destination (also one of the sources, for operations with 2 operands) can be of one of the following 4 types:

Register Mode: Register contents are operand
Indexed Mode: (Rn + X) points to the operand.

X is stored in the next word

Symbolic Mode: (PC + X) points to the operand.

X is stored in the next word. Indexed Mode X(PC) is used

Absolute Mode: The word following the instruction

contains the absolute address.

The source can be either one of the 3 above types or one of the types:

Indirect Register Mode: Rn is used as a pointer to the operand
Indirect Autoincrement: Rn is used as a pointer to the operand
Immediate Mode: The word following the instruction

contains the immediate constant N. Indirect Autoincrement Mode @PC+ is used

Of cause the type of addressing used effects execution time (register<->register is faster than memory<->memory), but doing operations with data memory as addresses is faster than first loading, then operating, then storing. Ex: Add from data mem. to data mem. is 6 cycles, add from reg to mem is 4. Move from mem to reg is 3.

Instruction set

A comprehensive list of operations and encoding can be found at Wikipedia

Comparison of instruction set architectures

	AVR	ARMv7	MSP430
Architecture	RISC	RISC	RISC
Machine type	Register-register	Register-register	Register-Register
Word size	8	32	16
Instruction size	16	32/16/mixed	16
Number of GP registers	32	13	12

References

https://en.wikipedia.org/wiki/Armv7 http://web.eecs.umich.edu/~prabal/teaching/eecs373-f10/readings/ARMv7-M_ARM.pdf https://web.eecs.umich.edu/~prabal/teaching/eecs373-f10/readings/ARM_Architecture_Overview.pdf

http://www.atmel.com/images/doc0856.pdf https://en.wikipedia.org/wiki/Atmel_AVR http://www.ti.com/sc/docs/products/micro/msp430/userguid/as_5.pdf https://en.wikipedia.org/wiki/TI_MSP430 https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set

[atmel_avr-1] ttp://www.atmel.com/products/microcontrollers/avr/

[wiki_avr-2] ttps://en.wikipedia.org/wiki/Atmel_AVR

[3] ttps://en.wikipedia.org/wiki/Atmel_AVR#Program_execution

[4] ttps://en.wikipedia.org/wiki/Armv7#Registers

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