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Computer Architecture Lab/Winter2006/SHWH/Detailed description

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Tante Emma - Processor Description edit

Features edit

  • 16-bit RISC processor
  • Harvard architecture
  • 40 instructions
  • 3 pipeline stages
  • 16 16-bit GPRs
  • 16-bit internal and external bus
  • Fix instruction width
  • Little Endian number format

Instruction Set edit

Arithmetic and Logic Instructions edit

Instruction Operation Opcode Flags Description
ADD rA, rB rA   rA + rB 0b000000 C,Z Add without Carry
ADDC rA, rB rA   rA + rB + C 0b100110 C,Z Add with Carry
SUB rA, rB Ra   rA - rB 0b000001 C,Z Subtract without Carry
SUBC rA, rB Ra   rA - rB - C 0b100111 C,Z Subtract with Carry
AND rA, rB rA   rA   rB 0b000010 Z Logical AND
OR rA, rB rA   rA   rB 0b000011 Z Logical OR
XOR rA, rB rA   rA   rB 0b000100 Z Exclusive OR
NEG rA rA   0x00 - rA 0b000101 Z,C Two's Complement
INC rA rA   rA + 1 0b000110 Z Increment
DEC rA rA   rA + 1 0b000111 Z Decrement
CLR rA rA   rA   rA 0b001000 Z Clear register
SET rA rA   0xFF 0b001001 None Set register
MUL rA, rB r2:r1   rA   rB 0b001010 Z,C Multiply unsigned
DIV rA, rB r2:r1   rA / rB 0b001011 Z,C Divide unsigned

Branch Instructions edit

Instruction Operation Opcode Flags Description
CALL Stack   PC 0b001100 None Call subroutine
JUMP PC   Stack ?? 0b001101 None Jump
RET PC   Stack 0b001110 None Return from subroutine
CMP rA, rB rA - rB 0b001111 Z,L,G Compare
CMPSKIP rA, rB if (rA == rB) PC   PC + 2 0b010000 None Compare, skip if equal
BRZ if (Z == 1) then PC   PC + Stack + 1 0b010001 None Branch, if zero
BRNZ if (Z == 0) then PC   PC + Stack + 1 0b010010 None Branch, if not zero
BRL if (L == 1) then PC   PC + Stack + 1 0b010011 None Branch, if lower
BRNL if (L == 0) then PC   PC + Stack + 1 0b010100 None Branch, if not lower
BRG if (G == 1) then PC   PC + Stack + 1 0b010101 None Branch, if greater
BRNG if (G == 0) then PC   PC + Stack + 1 0b010110 None Branch, if not greater

Data Transfer Instructions edit

Instruction Operation Opcode Flags Description
MOV rA, rB rA   rB 0b010111 None Copy Register
LDI rA, constant rA   constant 0b011000 None Load immediate
LD rA, rB rA   (rB) 0b011001 None Load
ST rA, rB (rA)   rB 0b011010 None Store
IN rA, PORT rA   PORT 0b011011 None In from I/O location
OUT rA, PORT PORT   rA 0b011100 None Out from I/O location
POP rA rA   Stack 0b011101 None Pop register from Stack; The Stack Pointer is pre-incremented by 1 before POP
PUSH rA Stack   rA 0b011110 None Push register on stack; The Stack Pointer is post-decremented by one after PUSH

Bit and Bit-test Instructions edit

Instruction Operation Opcode Flags Description
SHL rA rA(n+1)   rA(n), rA(0)   0, C   rA(7) 0b011111 Z,C Logical shift left
SHR rA rA(n)   rA(n+1), rA(7)  0, C   rA(0) 0b100000 Z,C Logical shift right
ASL rA rA(n+1)   rA(n), n = 0,...,6 0b100001 Z,C Arithmetic shift left
ASR rA rA(n)   rA(n+1), n = 0,...,6 0b100010 Z,C Arithmetic shift right
ROL rA rA(0)   C, rA(n+1)   rA(n), C   rA(7) 0b100011 Z,C Rotate left through Carry
ROR rA rA(7)   C, rA(n)   rA(n+1), C   rA(0) 0b100100 Z,C Rotate right through Carry

MCU Control Instruction edit

Instruction Operation Opcode Flags Description
NOP 0b100101 None No Operation

Status Register edit

Flag Abbreviation Default Description
Zero Z 0
Lesser L 0
Greater G 0
Carry C 0

Instruction Format edit

Bits 0-7 8-15 16-31
Content Opcode Register Immediate or Unused

or

Bits 0-7 8-15 16-23 24-31
Content Opcode Register A Register B Unused

or

Bits 0-7 8-31
Content Opcode Unused

Pipeline edit

Our processor "Tante Emma" has 3 pipeline stages:

  • Instruction fetch
  • Instruction decode
  • Execute
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